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ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
16 years 1 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
15 years 11 months ago
Towards a formal semantics for the AADL behavior annex
—AADL is an Architecture Description Language which describes embedded real-time systems. Behavior annex is an extension of the dispatch mechanism of AADL execution model. This p...
Zhibin Yang, Kai Hu, Dianfu Ma, Lei Pi
ICRA
2009
IEEE
141views Robotics» more  ICRA 2009»
15 years 10 months ago
Development of insect thorax based flapping mechanism
—Design of a flapping mechanism for flapping wing micro air vehicles (FWMAV) is presented based on a mathematical model of insect thorax. This model also includes an aerodynami...
Zaeem Khan, Kyle Steelman, Sunil Agrawal
INFOCOM
2006
IEEE
15 years 10 months ago
TCP NewReno Throughput in the Presence of Correlated Losses: The Slow-but-Steady Variant
— This paper presents an analytical model of steady state throughput of the Slow-but-Steady variant of TCP NewReno as a function of loss event rate, average number of segments lo...
Roman Dunaytsev, Yevgeni Koucheryavy, Jarmo Harju
UML
2004
Springer
15 years 9 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...