6229 search results - page 13 / 1246 » Models of Computation for Networks on Chip |
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
PDP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
IJCNN
2007
IEEE
14 years 1 months ago
2007
IEEE
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
MASCOTS
2007
2007
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
13 years 9 months ago
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...
SAC
2006
ACM
14 years 1 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...