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» Models of Computation for Networks on Chip
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FPL
2006
Springer
242views Hardware» more  FPL 2006»
14 years 24 days ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
IPPS
2008
IEEE
14 years 3 months ago
Immersive real-time large-scale network simulation: A research summary
Immersive real-time large-scale network simulation is a technique that supports simulation of large-scale networks to interact with real implementations of network protocols, netw...
Jason Liu
AIMS
2007
Springer
14 years 3 months ago
Graph Models of Critical Infrastructure Interdependencies
Critical infrastructures are interconnected on multiple levels, and due to their size models with acceptable computational complexity and adequate modeling capacities must be devel...
Nils Kalstad Svendsen, Stephen D. Wolthusen
ICCCN
2008
IEEE
14 years 3 months ago
Sources and Monitors: A Trust Model for Peer-to-Peer Networks
—In this paper, we introduce an objective model of trust in peer-to-peer networks. Based on this model, we develop protocols that can be used by the peers in a peer-to-peer netwo...
Yan Li, Mohamed G. Gouda
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
14 years 3 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass