6229 search results - page 192 / 1246 » Models of Computation for Networks on Chip |
NOCS
2009
IEEE
14 years 4 months ago
2009
IEEE
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...
DSN
2009
IEEE
2009
IEEE
Processor reliability enhancement through compiler-directed register file peak temperature reduction
14 years 1 months ago
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
SLIP
2003
ACM
14 years 2 months ago
2003
ACM
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
APNOMS
2006
Springer
14 years 29 days ago
2006
Springer
This paper intends to introduce the development of a terminal agent for QoS measurement that is suitable for an NGN environment, and to summarize the results of its performance tes...
APNOMS
2006
Springer
14 years 29 days ago
2006
Springer
Abstract. This paper presents a Bandwidth Broker (BB) based admission control and traffic engineering model for Diffserv supported MPLS networks. The proposed model uses a multi-pa...