6229 search results - page 19 / 1246 » Models of Computation for Networks on Chip |
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...
IJCNN
2000
IEEE
13 years 12 months ago
2000
IEEE
Selectiveattentionis a mechanismsused to sequentiallyselectthe spatiallocationsof salientregionsin the sensor’sfieldof view. This mechanism overcomesthe problem of flooding limi...
SBCCI
2005
ACM
14 years 1 months ago
2005
ACM
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
On-line routing strategies for communication in a dynamic network on chip (DyNoC) environment are presented. The DyNoC has been presented as a medium supporting communication amon...