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» Models of Computation for Networks on Chip
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DAC
2007
ACM
14 years 9 months ago
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation
We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and with...
Khaled R. Heloue, Navid Azizi, Farid N. Najm
MR
2002
100views Robotics» more  MR 2002»
13 years 8 months ago
No-flow underfill flip chip assembly--an experimental and modeling analysis
In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken b...
Hua Lu 0003, K. C. Hung, Stoyan Stoyanov, Chris Ba...
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 2 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...
SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
14 years 2 months ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
14 years 1 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...