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ESANN
2008
13 years 10 months ago
An FPGA-based model suitable for evolution and development of spiking neural networks
We propose a digital neuron model suitable for evolving and growing heterogeneous spiking neural networks on FPGAs using a piecewise linear approximation of the Quadratic Integrate...
Hooman Shayani, Peter J. Bentley, Andrew M. Tyrrel...
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 9 months ago
Efficient Macromodeling for On-Chip Interconnects
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
Qinwei Xu, Pinaki Mazumder
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 10 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
IPPS
2007
IEEE
14 years 3 months ago
Simulating Red Storm: Challenges and Successes in Building a System Simulation
Supercomputers are increasingly complex systems merging conventional microprocessors with system on a chip level designs that provide the network interface and router. At Sandia N...
Keith D. Underwood, Michael Levenhagen, Arun Rodri...
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
14 years 2 months ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli