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» Models of Computation for Networks on Chip
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NECO
2011
13 years 3 months ago
Learning a Generative Model of Images by Factoring Appearance and Shape
Nicolas Le Roux, Nicolas Heess, Jamie Shotton, Joh...
WS
2011
ACM
13 years 3 months ago
LexInfo: A declarative model for the lexicon-ontology interface
Philipp Cimiano, Paul Buitelaar, John McCrae, Mich...
IJCV
2012
11 years 11 months ago
Leveraging 3D City Models for Rotation Invariant Place-of-Interest Recognition
Georges Baatz, Kevin Köser, David M. Chen, Ra...
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 2 months ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore
CDES
2006
100views Hardware» more  CDES 2006»
13 years 10 months ago
Integrity and Integration Issues for Nano-Tube Based Interconnect Systems
: As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the...
Tulin Mangir