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» Models of Computation for Networks on Chip
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ICNP
2006
IEEE
14 years 3 months ago
Modeling Heterogeneous User Churn and Local Resilience of Unstructured P2P Networks
Zhongmei Yao, Derek Leonard, Xiaoming Wang, Dmitri...
RECOMB
2002
Springer
14 years 9 months ago
A bayesian approach to transcript estimation from gene array data: the BEAM technique
We present a new statistically optimal approach to estimate transcript levels and ratios from one or more gene array experiments. The Bayesian Estimation of Array Measurements (BE...
Ron O. Dror, Jonathan G. Murnick, Nicola A. Rinald...
ATVA
2008
Springer
131views Hardware» more  ATVA 2008»
13 years 11 months ago
Computation Tree Regular Logic for Genetic Regulatory Networks
Model checking has proven to be a useful analysis technique not only for concurrent systems, but also for the genetic regulatory networks (Grns) that govern the functioning of livi...
Radu Mateescu, Pedro T. Monteiro, Estelle Dumas, H...
DAC
2006
ACM
14 years 2 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
CORR
2010
Springer
146views Education» more  CORR 2010»
13 years 9 months ago
Building Computer Network Attacks
In this work we start walking the path to a new perspective for viewing cyberwarfare scenarios, by introducing conceptual tools (a formal model) to evaluate the costs of an attack...
Ariel Futoransky, Luciano Notarfrancesco, Gerardo ...