SystemC transaction level models and RTL verification

This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are being reused for RTL verification. The paper discusses how the task of system verification is changing as systems become more complex and it discusses how companies are striving to eliminate fragmentation within their design and verification flows by leveraging SystemC transaction level models. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids – simulation, verification. General Terms Standardization, Languages, Verification. Keywords SystemC, Transaction Level Model, TLM, RTL Verification, Hardware/Software Co-Design, Hardware/Software CoVerification.

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Stuart Swan
• Keywords: Computer Architecture, DAC 2006, Rtl Verification, SystemC Transaction Level, Transaction Level Model