Sciweavers

3454 search results - page 493 / 691
» Modern computer algebra
Sort
View
ICS
2004
Tsinghua U.
15 years 11 months ago
Effective stream-based and execution-based data prefetching
With processor speeds continuing to outpace the memory subsystem, cache missing memory operations continue to become increasingly important to application performance. In response...
Sorin Iacobovici, Lawrence Spracklen, Sudarshan Ka...
PARA
2004
Springer
15 years 11 months ago
Cache Optimizations for Iterative Numerical Codes Aware of Hardware Prefetching
Cache optimizations typically include code transformations to increase the locality of memory accesses. An orthogonal approach is to enable for latency hiding by introducing prefet...
Josef Weidendorfer, Carsten Trinitis
ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 11 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
DSN
2003
IEEE
15 years 11 months ago
A Voltage Scheduling Heuristic for Real-Time Task Graphs
Energy constrained complex real-time systems are becoming increasingly important in defense, space, and consumer applications. In this paper, we present a sensible heuristic to ad...
Diganta Roychowdhury, Israel Koren, C. Mani Krishn...
ICPP
2003
IEEE
15 years 11 months ago
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo...