6106 search results - page 205 / 1222 » Modes for Software Architectures |
ARITH
2007
IEEE
14 years 3 months ago
2007
IEEE
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
SRDS
2007
IEEE
14 years 3 months ago
2007
IEEE
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
ARITH
1999
IEEE
14 years 1 months ago
1999
IEEE
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
ISCA
1999
IEEE
14 years 1 months ago
1999
IEEE
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
FPGA
1997
ACM
14 years 1 months ago
1997
ACM
This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a network contr...