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DAC
2003
ACM
14 years 2 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
APCSAC
2004
IEEE
14 years 1 months ago
Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...
Philip Machanick
DT
2002
67views more  DT 2002»
13 years 9 months ago
A Retargetable Embedded In-Circuit Emulation Module for Microprocessors
This article presents an in-circuit emulation (ICE) module that can be embedded with a microprocessr core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typ...
Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching...
E4MAS
2006
Springer
14 years 1 months ago
A Reference Architecture for Situated Multiagent Systems
Abstract. A reference architecture integrates a set of architectural patterns that have proven their value for a family of applications. Such family of applications is characterize...
Danny Weyns, Tom Holvoet
WER
2001
Springer
14 years 2 months ago
Analysing the Tradeoffs Among Requirements, Architectures and COTS Components
The development of software systems from already built COTS components has been motivated by the prospect of reduced cost and development time. However, developing COTS-based syst...
Carina Alves, João Bosco Pinto Filho, Jaels...