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FPL
2007
Springer
98views Hardware» more  FPL 2007»
14 years 3 days ago
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel ...
Shannon Koh, Oliver Diessel
ERLANG
2008
ACM
14 years 2 days ago
Refactoring module structure
László Lövei, Csaba Hoch, Hanna...
FPL
2008
Springer
124views Hardware» more  FPL 2008»
13 years 12 months ago
Direct sigma-delta modulated signal processing in FPGA
The effectiveness of implementing bit-stream signal processing (BSSP) multiplier circuits in FPGAs, in terms of hardware resources and clock frequency, is presented. In particular...
Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-S...