Sciweavers

300 search results - page 31 / 60
» Multi Level Multiple Descriptions
Sort
View
ECTEL
2007
Springer
14 years 3 months ago
MACE - Enriching Architectural Learning Objects for Experience Multiplication
Education in architecture requires access to a broad range of learning materials to develop flexibility and creativity in design. The learning material is compromised of textual an...
Moritz Stefaner, Elisa Dalla Vecchia, Massimiliano...
ICPP
2009
IEEE
13 years 7 months ago
Thread Merging Schemes for Multithreaded Clustered VLIW Processors
Several multithreading techniques have been proposed to reduce the resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is ...
Manoj Gupta, Fermín Sánchez, Josep L...
ICIP
2002
IEEE
14 years 11 months ago
Semantics of multimedia in MPEG-7
In this paper, we present the tools standardized by MPEG-7 for describing the semantics of multimedia. In particular, we the Abstraction Model, entities, attributes and relations ...
A. Murat Tekalp, Ahmet Ekin, Alesandro Bugatti, An...
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 10 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
IPPS
2003
IEEE
14 years 2 months ago
Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor
The available Instruction Level Parallelism in Java bytecode (Java-ILP) is not readily exploitable using traditional in-order or out-of-order issue mechanisms due to dependencies ...
R. Achutharaman, R. Govindarajan, G. Hariprakash, ...