300 search results - page 43 / 60 » Multi Level Multiple Descriptions |
HPCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Mult...
INFOCOM
2005
IEEE
14 years 1 months ago
2005
IEEE
— In this paper, we present a novel packet delivery mechanism called Multi-path and Multi-Speed Routing Protocol (MMSPEED) for probabilistic QoS guarantee in wireless sensor netw...
ICS
2009
Tsinghua U.
13 years 12 months ago
2009
Tsinghua U.
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
FPGA
2004
ACM
14 years 23 days ago
2004
ACM
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
3DIM
1997
IEEE
13 years 11 months ago
1997
IEEE
For registration of 3-D free-form surfaces we have developed a representation which requires no knowledge of the transformation between views. The representation comprises descrip...