Sciweavers

575 search results - page 101 / 115
» Multi-Valued Logic Synthesis
Sort
View
DAC
2003
ACM
14 years 10 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
DAC
2003
ACM
14 years 10 months ago
Making cyclic circuits acyclic
Cyclic circuits that do not hold state or oscillate are often the most convenient representation for certain functions, such as arbiters, and can easily be produced inadvertently ...
Stephen A. Edwards
DAC
2003
ACM
14 years 10 months ago
Large-scale SOP minimization using decomposition and functional properties
In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, ...
Alan Mishchenko, Tsutomu Sasao
DAC
2003
ACM
14 years 10 months ago
Partial task assignment of task graphs under heterogeneous resource constraints
This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining assignment of these tas...
Radoslaw Szymanek, Krzysztof Kuchcinski
DAC
2005
ACM
14 years 10 months ago
Incremental exploration of the combined physical and behavioral design space
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Z...