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ISPD
2003
ACM
132views Hardware» more  ISPD 2003»
14 years 3 months ago
Architecture and synthesis for multi-cycle communication
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
CIIA
2009
13 years 11 months ago
Physical Synthesis for CPLD Architectures
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...
Sid-Ahmed Senouci
TCAD
2008
116views more  TCAD 2008»
13 years 9 months ago
Scalable Synthesis and Clustering Techniques Using Decision Diagrams
BDDs have proven to be an efficient means to represent and manipulate Boolean formulae [1] and sets [2] due to their compactness and canonicality. In this work, we leverage the eff...
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
CCE
2005
13 years 9 months ago
Logic-based outer approximation for globally optimal synthesis of process networks
Process network problems can be formulated as Generalized Disjunctive Programs where a logicbased representation is used to deal with the discrete and continuous decisions. A new ...
María Lorena Bergamini, Pío A. Aguir...
ACSD
2010
IEEE
239views Hardware» more  ACSD 2010»
13 years 8 months ago
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
W. B. Toms, David A. Edwards