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» Multi-level network optimization for low power
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DATE
2003
IEEE
97views Hardware» more  DATE 2003»
14 years 19 days ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
COMSUR
2011
196views Hardware» more  COMSUR 2011»
12 years 7 months ago
From MANET To IETF ROLL Standardization: A Paradigm Shift in WSN Routing Protocols
—In large networks, a data source may not reach the intended sink in a single hop, thereby requiring the traffic to be routed via multiple hops. An optimized choice of such rout...
Thomas Watteyne, Antonella Molinaro, Maria Grazia ...
ISCAS
2008
IEEE
125views Hardware» more  ISCAS 2008»
14 years 1 months ago
Ultra-low-power UWB for sensor network applications
— Long distance, low data-rate UWB communication for sensor network applications requires a highly energy efficient transceiver combined with circuit and system-level optimizati...
Patrick P. Mercier, Denis C. Daly, Manish Bhardwaj...
IWNAS
2008
IEEE
14 years 1 months ago
A Novel Embedded Accelerator for Online Detection of Shrew DDoS Attacks
∗ As one type of stealthy and hard-to-detect attack, lowrate TCP-targeted DDoS attack can seriously throttle the throughput of normal TCP flows for a long time without being noti...
Hao Chen, Yu Chen
DAC
2008
ACM
14 years 8 months ago
Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM
In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This...
Krishna Bharath, Ege Engin, Madhavan Swaminathan