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» Multi-level network optimization for low power
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GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
14 years 19 days ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...
ISCA
1998
IEEE
126views Hardware» more  ISCA 1998»
13 years 11 months ago
Switcherland: A QoS Communication Architecture for Workstation Clusters
Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today...
Hans Eberle, Erwin Oertli
ICPP
2006
IEEE
14 years 1 months ago
Parallel Algorithms for Evaluating Centrality Indices in Real-world Networks
This paper discusses fast parallel algorithms for evaluating several centrality indices frequently used in complex network analysis. These algorithms have been optimized to exploi...
David A. Bader, Kamesh Madduri
IPSN
2010
Springer
14 years 2 months ago
Online distributed sensor selection
A key problem in sensor networks is to decide which sensors to query when, in order to obtain the most useful information (e.g., for performing accurate prediction), subject to co...
Daniel Golovin, Matthew Faulkner, Andreas Krause
DAC
2002
ACM
14 years 8 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid