626 search results - page 58 / 126 » Multi-modular Associative Memory |
ISCA
2005
IEEE
14 years 3 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
ANCS
2005
ACM
14 years 3 months ago
2005
ACM
Hash tables provide efficient table implementations, achieving O(1), query, insert and delete operations at low loads. However, at moderate or high loads collisions are quite freq...
ISCA
2000
IEEE
14 years 2 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
EVOW
2008
Springer
13 years 11 months ago
2008
Springer
Abstract. This paper describes a memory enhanced evolutionary algorithm (EA) approach to the dynamic job shop scheduling problem. Memory enhanced EAs have been widely investigated ...
ISCA
1997
IEEE
14 years 2 months ago
1997
IEEE
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....