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ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 4 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
ICDCS
2005
IEEE
14 years 1 months ago
Handling Asymmetry in Power Heterogeneous Ad Hoc Networks: A Cross Layer Approach
Power heterogeneous ad hoc networks are characterized by link layer asymmetry: the ability of lower power nodes to receive transmissions from higher power nodes but not vice versa...
Vasudev Shah, Srikanth V. Krishnamurthy
ICPP
2007
IEEE
14 years 2 months ago
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
As the number of computing and storage nodes keeps increasing, the interconnection network is becoming a key element of many computing and communication systems, where the overall...
Gaspar Mora, Pedro Javier García, Jose Flic...
IMC
2007
ACM
13 years 9 months ago
Quality-of-service class specific traffic matrices in ip/mpls networks
In this paper we consider the problem of determining traffic matrices for end-to-end demands in an IP/MPLS network that supports multiple quality of service (QoS) classes. More pr...
Stefan Schnitter, Franz Hartleb, Martin Horneffer
SIGARCH
2008
107views more  SIGARCH 2008»
13 years 7 months ago
A lightweight streaming layer for multicore execution
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
David Zhang, Qiuyuan J. Li, Rodric Rabbah, Saman A...