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PC
2000
100views Management» more  PC 2000»
13 years 8 months ago
Trading accuracy for speed in parallel simulated annealing with simultaneous moves
A common approach to parallelizing simulated annealing to generate several perturbations to the current solution simultaneously, requiring synchronization to guarantee correct eva...
M. D. Durand, Steve R. White
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
12 years 11 months ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
CODES
2007
IEEE
14 years 2 months ago
HySim: a fast simulation framework for embedded software development
Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology,...
Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leu...
CHES
2009
Springer
150views Cryptology» more  CHES 2009»
14 years 3 months ago
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
Francesco Regazzoni, Alessandro Cevrero, Fran&cced...
ASPLOS
2008
ACM
13 years 10 months ago
Streamware: programming general-purpose multicore processors using streams
Recently, the number of cores on general-purpose processors has been increasing rapidly. Using conventional programming models, it is challenging to effectively exploit these core...
Jayanth Gummaraju, Joel Coburn, Yoshio Turner, Men...