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IEEEPACT
2002
IEEE
14 years 8 days ago
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
Jaewook Shin, Jacqueline Chame, Mary W. Hall
VEE
2006
ACM
139views Virtualization» more  VEE 2006»
14 years 1 months ago
Vector LLVA: a virtual vector instruction set for media processing
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speciï¬...
Robert L. Bocchino Jr., Vikram S. Adve
IEEEPACT
2000
IEEE
13 years 11 months ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
14 years 1 months ago
Performance improvement of the H.264/AVC deblocking filter using SIMD instructions
The H.264/AVC standard defines an in-loop de- instructions, available in current multimedia SIMD instruction blocking filter which is used in both the encoder and decoder. This set...
Stephen Warrington, Hassan Shojania, Subramania Su...
HPCA
1999
IEEE
13 years 11 months ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi