149 search results - page 20 / 30 » Multiple Flows of Control in Migratable Parallel Programs |
RTSS
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
SASP
2009
IEEE
14 years 3 months ago
2009
IEEE
—Multi-cycle Instruction set extensions (ISE) can be pipelined in order to increase their throughput; however, typical program traces seldom contain consecutive calls to the same...
DATE
2010
IEEE
14 years 28 days ago
2010
IEEE
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
MICRO
1998
IEEE
14 years 25 days ago
1998
IEEE
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
ADT
2011
13 years 6 days ago
2011
Currently, there is a strong effort of the research community in rethinking the Internet architecture to cope with its current limitations and support new requirements. Many resea...