Sciweavers

377 search results - page 17 / 76
» Multiple Instruction Stream Processor
Sort
View
SACRYPT
2001
Springer
106views Cryptology» more  SACRYPT 2001»
14 years 3 days ago
Fast Normal Basis Multiplication Using General Purpose Processors
—For cryptographic applications, normal bases have received considerable attention, especially for hardware implementation. In this article, we consider fast software algorithms ...
Arash Reyhani-Masoleh, M. Anwarul Hasan
ASPLOS
2010
ACM
14 years 2 months ago
MacroSS: macro-SIMDization of streaming applications
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...
Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Ku...
ISCAPDCS
2001
13 years 9 months ago
A Multiple Blocks Fetch Engine for High Performance Superscalar Processors
The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one bra...
Yung-Chung Wu, Jong-Jiann Shieh
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 1 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
PLDI
2000
ACM
14 years 1 days ago
Dynamo: a transparent dynamic optimization system
We describe the design and implementation of Dynamo, a software dynamic optimization system that is capable of transparently improving the performance of a native instruction stre...
Vasanth Bala, Evelyn Duesterwald, Sanjeev Banerjia