377 search results - page 21 / 76 » Multiple Instruction Stream Processor |
ISCA
1997
IEEE
13 years 12 months ago
1997
IEEE
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
MICRO
1991
IEEE
13 years 11 months ago
1991
IEEE
- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processor...
INFOVIS
1999
IEEE
13 years 12 months ago
1999
IEEE
The advent of superscalar processors with out-of-order execution makes it increasingly difficult to determine how well an application is utilizing the processor and how to adapt t...
ECRTS
2007
IEEE
14 years 2 months ago
2007
IEEE
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
HIPC
2000
Springer
13 years 11 months ago
2000
Springer
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...