377 search results - page 35 / 76 » Multiple Instruction Stream Processor |
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
ICCD
2000
IEEE
14 years 4 months ago
2000
IEEE
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
LCPC
1998
Springer
13 years 12 months ago
1998
Springer
Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved...
Presentation
Data-parallel architectures like SIMD (Single Instruction Multiple Data) or SIMT (Single Instruction Multiple Thread) have been adopted in many recent CPU and GPU architectures. Al...