377 search results - page 41 / 76 » Multiple Instruction Stream Processor |
ISPASS
2006
IEEE
14 years 3 months ago
2006
IEEE
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
ASAP
2003
IEEE
14 years 2 months ago
2003
IEEE
Symmetric-key block ciphers encrypt data, providing data confidentiality over the public Internet. For inter-operability reasons, it is desirable to support a variety of symmetric...
DSN
2005
IEEE
13 years 11 months ago
2005
IEEE
The increasing transient fault rate will necessitate onchip fault tolerance techniques in future processors. The speed gap between the processor and the memory is also increasing,...
DSD
2008
IEEE
14 years 3 months ago
2008
IEEE
While shrinking geometries of embedded LSI devices is beneficial for portable intelligent systems, it is increasingly susceptible to influences from electrical noise, process vari...
RTSS
2002
IEEE
14 years 1 months ago
2002
IEEE
Simultaneous multithreading (SMT) improves processor throughput by processing instructions from multiple threads each cycle. This is the first work to explore soft real-time sche...