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ERSA
2004
106views Hardware» more  ERSA 2004»
13 years 9 months ago
QOS Aware HW/SW Partitioning on Run-time Reconfigurable Multimedia Platforms
Advanced multimedia applications (e.g. based on MPEG-4) will consist of multiple scalable multimedia objects. This scalability enables the application to adapt to different proces...
Nam Pham Ngoc, Gauthier Lafruit, Jean-Yves Mignole...
TPDS
2010
144views more  TPDS 2010»
13 years 6 months ago
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
David A. Zier, Ben Lee
ARC
2012
Springer
280views Hardware» more  ARC 2012»
12 years 3 months ago
Scalable Memory Hierarchies for Embedded Manycore Systems
As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typica...
Sen Ma, Miaoqing Huang, Eugene Cartwright, David L...
HPCA
2007
IEEE
14 years 8 months ago
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlk...
CASES
2006
ACM
13 years 11 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...