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» Multiple Instruction Stream Processor
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PPOPP
2009
ACM
14 years 8 months ago
Comparability graph coloring for optimizing utilization of stream register files in stream processors
A stream processor executes an application that has been decomposed into a sequence of kernels that operate on streams of data elements. During the execution of a kernel, all stre...
Xuejun Yang, Li Wang, Jingling Xue, Yu Deng, Ying ...
ISCA
2009
IEEE
150views Hardware» more  ISCA 2009»
14 years 2 months ago
Stream chaining: exploiting multiple levels of correlation in data prefetching
Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetc...
Pedro Diaz, Marcelo Cintra
ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
13 years 11 months ago
Impact of Sharing-Based Thread Placement on Multithreaded Architectures
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
Radhika Thekkath, Susan J. Eggers
IPPS
2003
IEEE
14 years 28 days ago
Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor
The available Instruction Level Parallelism in Java bytecode (Java-ILP) is not readily exploitable using traditional in-order or out-of-order issue mechanisms due to dependencies ...
R. Achutharaman, R. Govindarajan, G. Hariprakash, ...
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
13 years 12 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin