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ICPP
1999
IEEE
14 years 7 days ago
SLC: Symbolic Scheduling for Executing Parameterized Task Graphs on Multiprocessors
Task graph scheduling has been found effective in performance prediction and optimization of parallel applications. A number of static scheduling algorithms have been proposed for...
Michel Cosnard, Emmanuel Jeannot, Tao Yang
ISCAPDCS
2003
13 years 9 months ago
Loop Transformation Techniques To Aid In Loop Unrolling and Multithreading
In modern computer systems loops present a great deal of opportunities for increasing Instruction Level and Thread Level Parallelism. Loop unrolling is a technique used to obtain ...
Litong Song, Yuhua Zhang, Krishna M. Kavi
MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
14 years 10 days ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 2 months ago
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures
As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify ...
Nicolas Coste, Hubert Garavel, Holger Hermanns, Ri...
POPL
1998
ACM
14 years 5 days ago
Secure Information Flow in a Multi-Threaded Imperative Language
Previously, we developed a type system to ensure secure information flow in a sequential, imperative programming language [VSI96]. Program variables are classified as either hig...
Geoffrey Smith, Dennis M. Volpano