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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 2 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ISCA
1997
IEEE
113views Hardware» more  ISCA 1997»
13 years 11 months ago
Effects of Communication Latency, Overhead, and Bandwidth in a Cluster Architecture
This work provides a systematic study of the impact of communication performance on parallelapplications in a high performance network of workstations. We develop an experimental ...
Richard P. Martin, Amin Vahdat, David E. Culler, T...
ICCNMC
2005
Springer
14 years 1 months ago
Available Bandwidth Measurement Schemes over Networks
In next generation network (NGN), end-to-end QoS is one of the critical issues for real-time multimedia communications and applications. Such applications are sensitive to the avai...
Fang Qi, Jin Zheng, Weijia Jia, Guojun Wang
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
14 years 1 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
TVLSI
2008
157views more  TVLSI 2008»
13 years 7 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung