117 search results - page 13 / 24 » NOC architecture design for multi-cluster chips |
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-onChip (...
DSN
2006
IEEE
14 years 1 months ago
2006
IEEE
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
RTCSA
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents the concepts of switching in the Time-Triggered Network-on-Chip (TTNoC), which is the communication subsystem of the Time-Triggered Systemon-Chip (TTSoC) archi...
IESS
2007
Springer
14 years 1 months ago
2007
Springer
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
NOCS
2009
IEEE
14 years 2 months ago
2009
IEEE
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...