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IPPS
2006
IEEE
14 years 2 months ago
Wire-speed total order
— Many distributed systems may be limited in their performance by the number of transactions they are able to support per unit of time. In order to achieve fault tolerance and to...
Tal Anker, Danny Dolev, G. Greenman, I. Shnaiderma...
ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
14 years 24 days ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram
IPPS
1998
IEEE
14 years 22 days ago
Jacobi Orderings for Multi-Port Hypercubes
1 The communication cost plays a key role in the performance of many parallel algorithms. In the particular case of the one-sided Jacobi method for symmetric eigenvalue and eigenve...
Dolors Royo, Antonio González, Miguel Valer...
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
14 years 1 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba
COR
2006
62views more  COR 2006»
13 years 8 months ago
Optimal batting orders in one-day cricket
This paper concerns the search for optimal or nearly optimal batting orders in one-day cricket. A search is conducted over the space of permutations of batting orders where simula...
Tim B. Swartz, Paramjit S. Gill, David Beaudoin, B...