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ARITH
2005
IEEE
15 years 8 months ago
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
Silvia M. Müller, Christian Jacobi 0002, Hwa-...
ISCAS
2005
IEEE
143views Hardware» more  ISCAS 2005»
15 years 8 months ago
Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation
— In this paper, we design and implement an improved hardware-based evolutionary digital filter (EDF) version 2. The EDF is an adaptive digital filter which is controlled by ad...
Masahide Abe, Hiroki Arai, Masayuki Kawamata
115
Voted
ITCC
2005
IEEE
15 years 8 months ago
Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography
1 Table lookups are one of the most frequently-used operations in symmetric-key ciphers. Particularly in the newer algorithms such as the Advanced Encryption Standard (AES), we fr...
A. Murat Fiskiran, Ruby B. Lee
ISAAC
2005
Springer
97views Algorithms» more  ISAAC 2005»
15 years 8 months ago
A Min-Max Relation on Packing Feedback Vertex Sets
Let G be a graph with a nonnegative integral function w defined on V (G). A collection F of subsets of V (G) (repetition is allowed) is called a feedback vertex set packing in G ...
Xujin Chen, Guoli Ding, Xiaodong Hu, Wenan Zang
148
Voted
DAC
2003
ACM
15 years 7 months ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...