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VTS
2005
IEEE
89views Hardware» more  VTS 2005»
14 years 2 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
MSV
2004
13 years 10 months ago
S(b)-Trees: An Optimal Balancing of Variable Length Keys
The paper studies the problem of maintaining external dynamic dictionaries with variable length keys. We introduce a new type of balanced trees, called S(b)-trees, which generaliz...
Konstantin V. Shvachko
ECSQARU
2005
Springer
14 years 2 months ago
On the Use of Restrictions for Learning Bayesian Networks
In this paper we explore the use of several types of structural restrictions within algorithms for learning Bayesian networks. These restrictions may codify expert knowledge in a g...
Luis M. de Campos, Javier Gomez Castellano
KDD
2006
ACM
156views Data Mining» more  KDD 2006»
14 years 9 months ago
Unsupervised learning on k-partite graphs
Various data mining applications involve data objects of multiple types that are related to each other, which can be naturally formulated as a k-partite graph. However, the resear...
Bo Long, Xiaoyun Wu, Zhongfei (Mark) Zhang, Philip...
GECCO
2006
Springer
202views Optimization» more  GECCO 2006»
14 years 11 days ago
Inference of genetic networks using S-system: information criteria for model selection
In this paper we present an evolutionary approach for inferring the structure and dynamics in gene circuits from observed expression kinetics. For representing the regulatory inte...
Nasimul Noman, Hitoshi Iba