Synthesis of Low Power CED Circuits Based on Parity Codes

An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code followed by structure constrained logic optimization that produces a circuit in which all single point faults are guaranteed to be detected. Two new contributions over previous work include (1) the use of a k-way partitioning algorithm combined with local search to select a parity-check code, and (2) a methodology for minimizing power consumption in the CED circuitry. Results indicate significant reductions in area overhead due to the new code selection procedure as well as the ability to find low power implementations for use in power conscious applications.

• Type: Conference
• Year: 2005
• Where: VTS
• Authors: Shalini Ghosh, Sugato Basu, Nur A. Touba
• Keywords: Low Power, Parity-check Code, Power Concurrent Error, VTS 2005