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ISNN
2007
Springer
15 years 10 months ago
A Hierarchical Self-organizing Associative Memory for Machine Learning
This paper proposes novel hierarchical self-organizing associative memory architecture for machine learning. This memory architecture is characterized with sparse and local interco...
Janusz A. Starzyk, Haibo He, Yue Li
CODES
2002
IEEE
15 years 9 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
BSN
2009
IEEE
307views Sensor Networks» more  BSN 2009»
15 years 11 months ago
Green and Sustainable Cyber-Physical Security Solutions for Body Area Networks
—Wireless sensor-based Body Area Networks (BAN) can play a major role in providing individualized health-care. Given their limited power sources, sensors in BAN have to be energy...
Krishna K. Venkatasubramanian, Ayan Banerjee, Sand...
SBACPAD
2006
IEEE
148views Hardware» more  SBACPAD 2006»
15 years 10 months ago
Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference
We present a scalable parallel implementation for converting a Bayesian network to a junction tree, which can then be used for a complete parallel implementation for exact inferen...
Vasanth Krishna Namasivayam, Animesh Pathak, Vikto...
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
15 years 10 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic