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SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
14 years 1 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...
WSC
2000
13 years 9 months ago
SNOOPy Calendar Queue
Discrete event simulations often require a future event list structure to manage events according to their timestamp. The choice of an efficient data structure is vital to the per...
Kah Leong Tan, Ian Li-Jin Thng

Publication
490views
15 years 6 months ago
Performance Testing Effort at the ATM Forum: An Overview
The testing group at ATM Forum is working on developing a specification for performance testing of ATM switches and networks. The emphasis is on the user perceived frame-level perf...
Raj Jain and Gojko Babic
ICNSC
2007
IEEE
14 years 2 months ago
A calibration test of Stewart platform
—A whole calibration test process of Stewart platform including the error analysis, calibration model, measure process, data analysis, parameter errors determination and the iter...
Yong Zhang, Feng Gao
MSWIM
2006
ACM
14 years 1 months ago
Testing methodology for an ad hoc routing protocol
In this paper, we define a model of an ad hoc routing protocol, i.e. the OLSR (Optimized Link-State Routing) protocol. This model handles novel constraints related to such networ...
Stéphane Maag, Fatiha Zaïdi