This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Discrete event simulations often require a future event list structure to manage events according to their timestamp. The choice of an efficient data structure is vital to the per...
The testing group at ATM Forum is working on developing a specification for performance testing of ATM switches and networks. The emphasis is on the user perceived frame-level perf...
—A whole calibration test process of Stewart platform including the error analysis, calibration model, measure process, data analysis, parameter errors determination and the iter...
In this paper, we define a model of an ad hoc routing protocol, i.e. the OLSR (Optimized Link-State Routing) protocol. This model handles novel constraints related to such networ...