Sciweavers

46 search results - page 4 / 10
» Network-on-Chip: The Intelligence is in The Wire
Sort
View
TVLSI
2010
13 years 2 months ago
Asynchronous Current Mode Serial Communication
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam ...
TSP
2010
13 years 2 months ago
Adaptive precoding for downstream crosstalk precancelation in DSL systems using sign-error feedback
The performance of many very high bit rate digital subscriber line (VDSL) systems is limited by the effects of crosstalk among the wires in a bundle. For the downstream, a precoder...
Jérôme Louveaux, Alle-Jan van der Vee...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 1 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
ICDCN
2010
Springer
14 years 2 months ago
An Intelligent IT Infrastructure for the Future
The proliferation of new modes of communication and collaboration has resulted in an explosion of digital information. To turn this challenge into an opportunity, the IT industry ...
Prith Banerjee
CSE
2009
IEEE
14 years 2 months ago
Intelligent Middleware for Adaptive Sensing of Tennis Coaching Sessions
—In professional tennis training matches, the coach needs to be able to view play from the most appropriate angle in order to monitor players activities. In this paper, we presen...
Richard Tynan, Anthony Schoofs, Conor Muldoon, Gre...