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» Network-on-Chip Architecture Exploration Framework
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DAC
2002
ACM
14 years 8 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
ACSD
2006
IEEE
148views Hardware» more  ACSD 2006»
14 years 1 months ago
Functional Model Exploration for Multimedia Applications via Algebraic Operators
An optimized functional design space exploration method for multimedia applications is proposed. The basis of the method is a way of representing the dependency and the concurrenc...
Shinjiro Kakita, Yosinori Watanabe, Douglas Densmo...
ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...
VLSI
2012
Springer
12 years 3 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
CCR
2004
100views more  CCR 2004»
13 years 7 months ago
A real options framework to value network, protocol, and service architecture
This paper proposes a real options framework for evaluating architectural choices and the economic value of these alternative choices of networks, protocols, and services. Using p...
Mark Gaynor, Scott Bradner