A framework for evaluating design tradeoffs in packet processing architectures

We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simulation, which tend to be infeasible when the design space is very large. We illustrate the feasibility of our method using a detailed case study. Categories and Subject Descriptors C.0 [Computer Systems Organization]: General--Modeling of computer architecture, System architectures; B.4.1 [Hardware]: Input/output and data communications--Data communication devices General Terms Performance, Design

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Lothar Thiele, Matthias Gries, Samarjit Chakraborty, Simon Künzli
• Keywords: DAC 2002, Design Automation, Design Space, Packet Processor Architectures, System Architectures