49 search results - page 6 / 10 » Neural Compiler Technology for a Parallel Architecture |
DAC
2003
ACM
14 years 9 months ago
2003
ACM
This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration. We have developed a compilation system that automatically ma...
SPAA
2006
ACM
14 years 2 months ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
HIPC
1999
Springer
14 years 26 days ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
IFIP
1998
Springer
14 years 24 days ago
1998
Springer
This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel an...
CGO
2010
IEEE
14 years 3 months ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...