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DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 2 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
JRTIP
2008
300views more  JRTIP 2008»
13 years 7 months ago
Real-time human action recognition on an embedded, reconfigurable video processing architecture
Abstract In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. Here we propose a realtime, emb...
Hongying Meng, Michael Freeman, Nick Pears, Chris ...
ICDCSW
2009
IEEE
14 years 2 months ago
Embedded Virtual Machines for Robust Wireless Control Systems
Embedded wireless networks have largely focused on openloop sensing and monitoring. To address actuation in closedloop wireless control systems there is a strong need to re-think ...
Rahul Mangharam, Miroslav Pajic
PODC
1994
ACM
13 years 11 months ago
A Performance Evaluation of Lock-Free Synchronization Protocols
In this paper, we investigate the practical performance of lock-free techniques that provide synchronization on shared-memory multiprocessors. Our goal is to provide a technique t...
Anthony LaMarca
ADT
2011
12 years 11 months ago
Virtual networks: isolation, performance, and trends
Currently, there is a strong effort of the research community in rethinking the Internet architecture to cope with its current limitations and support new requirements. Many resea...
Natalia Castro Fernandes, Marcelo D. D. Moreira, I...