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IPPS
2007
IEEE
14 years 3 months ago
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
Christopher Claus, Florian Helmut Müller, Joh...
GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden
CIS
2004
Springer
14 years 2 months ago
Mining Medline for New Possible Relations of Concepts
Scientific bibliographies in online databases provide a rich source of information for scientists in support of their research. In this paper, we propose a new method to predict po...
Wei Huang, Yoshiteru Nakamori, Shouyang Wang, Tiej...
ICIP
2008
IEEE
14 years 3 months ago
New optimized spline functions for interpolation on the hexagonal lattice
We propose new discrete-to-continuous interpolation models for hexagonally sampled data, that generalize two families of splines developed in the literature for the hexagonal latt...
Laurent Condat, Dimitri Van De Ville
ICML
2005
IEEE
14 years 9 months ago
New d-separation identification results for learning continuous latent variable models
Learning the structure of graphical models is an important task, but one of considerable difficulty when latent variables are involved. Because conditional independences using hid...
Ricardo Silva, Richard Scheines