144 search results - page 25 / 29 » New Non-Volatile Memory Structures for FPGA Architectures |
AAECC
2007
Springer
13 years 7 months ago
2007
Springer
Abstract. We present new performance models and a new, more compact data structure for cache blocking when applied to the sparse matrixvector multiply (SpM×V) operation, y ← y +...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
IEEEICCI
2007
IEEE
14 years 2 months ago
2007
IEEE
The ability to associate images is the basis for learning relationships involving vision, hearing, tactile sensation, and kinetic motion. A new architecture is described that has ...
CACM
2010
13 years 7 months ago
2010
Exploiting the multiprocessors that have recently become ubiquitous requires high-performance and reliable concurrent systems code, for concurrent data structures, operating syste...