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JRTIP
2008
249views more  JRTIP 2008»
13 years 7 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...
CODES
2003
IEEE
14 years 29 days ago
A low-cost memory architecture with NAND XIP for mobile embedded systems
NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and ...
Chanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Kim, ...
IPPS
2010
IEEE
13 years 5 months ago
MMT: Exploiting fine-grained parallelism in dynamic memory management
Dynamic memory management is one of the most expensive but ubiquitous operations in many C/C++ applications. Additional features such as security checks, while desirable, further w...
Devesh Tiwari, Sanghoon Lee, James Tuck, Yan Solih...
DAC
1997
ACM
13 years 12 months ago
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy
In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. This method rst synthesizes a design speci cation in a ne-grained way ...
Wen-Jong Fang, Allen C.-H. Wu
FPL
2004
Springer
95views Hardware» more  FPL 2004»
14 years 1 months ago
Improving FPGA Performance and Area Using an Adaptive Logic Module
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay...
Michael Hutton, Jay Schleicher, David M. Lewis, Br...