Sciweavers

73 search results - page 10 / 15
» New Results on Instruction Cache Attacks
Sort
View
MICRO
2006
IEEE
82views Hardware» more  MICRO 2006»
14 years 1 months ago
Yield-Aware Cache Architectures
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonath...
FSE
2006
Springer
117views Cryptology» more  FSE 2006»
13 years 11 months ago
How Far Can We Go on the x64 Processors?
This paper studies the state-of-the-art software optimization methodology for symmetric cryptographic primitives on the new 64-bit x64 processors, AMD Athlon64 (AMD64) and Intel Pe...
Mitsuru Matsui
CGO
2007
IEEE
14 years 1 months ago
Ubiquitous Memory Introspection
Modern memory systems play a critical role in the performance of applications, but a detailed understanding of the application behavior in the memory system is not trivial to atta...
Qin Zhao, Rodric M. Rabbah, Saman P. Amarasinghe, ...
SBACPAD
2005
IEEE
139views Hardware» more  SBACPAD 2005»
14 years 29 days ago
Chained In-Order/Out-of-Order DoubleCore Architecture
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...
Miquel Pericàs, Adrián Cristal, Rube...
CASES
2010
ACM
13 years 5 months ago
Implementing virtual secure circuit using a custom-instruction approach
Although cryptographic algorithms are designed to resist at least thousands of years of cryptoanalysis, implementing them with either software or hardware usually leaks additional...
Zhimin Chen, Ambuj Sinha, Patrick Schaumont