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102
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ARITH
2007
IEEE
15 years 9 months ago
P6 Binary Floating-Point Unit
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
Son Dao Trong, Martin S. Schmookler, Eric M. Schwa...
102
Voted
ASAP
2007
IEEE
95views Hardware» more  ASAP 2007»
15 years 9 months ago
Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
Sumit D. Mediratta, Jeffrey T. Draper
115
Voted
DSN
2007
IEEE
15 years 9 months ago
Multiprocessors May Reduce System Dependability under File-Based Race Condition Attacks
Attacks exploiting race conditions have been considered rare and “low risk”. However, the increasing popularity of multiprocessors has changed this situation: instead of waiti...
Jinpeng Wei, Calton Pu
ESCIENCE
2007
IEEE
15 years 9 months ago
Towards a Grid-Enabled Simulation Framework for Nano-CMOS Electronics
The electronics design industry is facing major challenges as transistors continue to decrease in size. The next generation of devices will be so small that the position of indivi...
Liangxiu Han, Asen Asenov, Dave Berry, Campbell Mi...
134
Voted
HICSS
2007
IEEE
124views Biometrics» more  HICSS 2007»
15 years 9 months ago
POSAML: A Visual Modeling Framework for Middleware Provisioning
Effective provisioning of next generation distributed applications hosted on diverse middleware platforms incurs significant challenges due to the applications’ growing complex...
Dimple Kaul, Arundhati Kogekar, Aniruddha S. Gokha...